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Field-programmable gate array
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51	1160 IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS FOR VIDEO TECHNOLOGY, VOL. 12, NO. 12, DECEMBER 2002 Transactions Letters________________________________________________________________ Efficient and Configurable Full-Se Add to Reading List Source URL: www.inesc-id.pt Language: English - Date: 2005-11-28 09:11:59 Parallel computing Video compression Block-matching algorithm Inter frame Field-programmable gate array Systolic array VHDL Cell Motion compensation Asynchronous array of simple processors
52	Compact and On-the-Fly Secure Dynamic Reconfiguration for Volatile FPGAs HIRAK KASHYAP and RICARDO CHAVES, INESC-ID, IST, Universidade de Lisboa The dynamic partial reconfiguration functionality of FPGAs can be attacked, Add to Reading List Source URL: www.inesc-id.pt Language: English - Date: 2016-02-23 14:14:05 Reconfigurable computing Fabless semiconductor companies Field-programmable gate array Disk encryption Xilinx Altera Virtex Bitstream Data Encryption Standard Galois/Counter Mode Encryption BitLocker
53	P4FPGA: High Level Synthesis for Networking Han Wang, Ki Suh Lee, Vishal Shrivastav, Hakim Weatherspoon Cornell University 1 Introduction Add to Reading List Source URL: conferences.sigcomm.org Language: English - Date: 2016-08-02 16:10:05 Computer networking P4 Field-programmable gate array Packet processing Hardware description language Xilinx Network interface controller Domain-specific language Verilog
54	D:E_FINALinated-pdf-Finalfilesdcad10-paginated-pdfsd-lind-linproof.dvi Add to Reading List Source URL: www-isl.stanford.edu Language: English - Date: 2013-02-27 17:04:20 Electronic design automation Integrated circuits Logic block Reconfigurable computing Fabless semiconductor companies Field-programmable gate array Placement Virtex Routing Place and route Altera Image segmentation
55	RISC-V on Sakura-G Advisor(s): Thomas Unterluggauer Institute for Applied Information Processing and Communications (IAIK) Graz University of Technology, Austria Motivation Add to Reading List Source URL: www.iaik.tugraz.at Language: English - Date: 2015-09-08 06:00:03 Instruction set architectures Reconfigurable computing Fabless semiconductor companies Xilinx Field-programmable gate array RISC-V Reduced instruction set computing
56	1300 Henley Court Pullman, WA6306 www.digilentinc.com Nexys Video™ FPGA Board Reference Manual Add to Reading List Source URL: www.europractice.stfc.ac.uk Language: English - Date: 2016-02-25 10:46:40 Integrated circuits Reconfigurable computing Field-programmable gate array JTAG Xilinx Serial Peripheral Interface Bus USB Programmer ICE Minimig Atmel AVR
57	CS:APP2e Web Aside ARCH:VLOG Verilog Implementation of a Pipelined Y86 Processor∗ Randal E. Bryant David R. O’Hallaron June 5, 2012 Add to Reading List Source URL: csapp.cs.cmu.edu Language: English - Date: 2012-06-05 05:37:00 Hardware description languages Electronic design automation Verilog Digital electronics Field-programmable gate array High-level synthesis Verilog-AMS SystemVerilog
58	Francisco Rodriguez-Henriquez, Centro de Investigación y de Estudios Avanzados del IPN (CINVESTAV), Col. San Pedro Zacatenco, Mexico D.F., Mexico; Nazar Abbas Saqib, Centro de Investigación y de Estudios Avanzados del Add to Reading List Source URL: delta.cs.cinvestav.mx Language: English - Date: 2007-02-03 23:20:56 CINVESTAV Instituto Politcnico Nacional Data Encryption Standard Cryptography Advanced Encryption Standard Algorithm Block cipher Field-programmable gate array Elliptic curve cryptography Reconfigurable computing Cryptographic engineering
59	ISSN No: International Journal & Magazine of Engineering, Technology, Management and Research A Peer Reviewed Open Access International Journal Add to Reading List Source URL: www.ijmetmr.com Language: English - Date: 2015-07-08 03:14:43 Image processing Reconfigurable computing Xilinx MicroBlaze Field-programmable gate array Background subtraction Soft microprocessor Embedded system Image segmentation Motion detection Coprocessor
60	Finding an adequate escape pod to real time Augmented Reality applications João Marcelo X. N. Teixeira, Veronica Teichrieb and Judith Kelner Virtual Reality and Multimedia Research Group Computer Science Center, Federal Add to Reading List Source URL: www.matmidia.mat.puc-rio.br Language: English - Date: 2009-12-09 18:55:18 Parallel computing GPGPU Graphics hardware OpenCL compute devices Fabless semiconductor companies Field-programmable gate array General-purpose computing on graphics processing units Compute kernel Connected-component labeling Graphics processing unit Coprocessor Altera Quartus

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